Application Mapping Scenarios onto Network on Chip Based Priority Lists

System on chip is a system consists of a number of intellectual property cores (IP cores) which are connected together utilizing electrical bus technology. When the number of IP cores increases, network on chip (NoC) architectures with regular topology instead of traditional bus based architecture are used. Mapping of IP cores on a given architecture is one of the three important topics of NOC design. In this paper, some heuristic mapping algorithms which map an application with a given task graph onto the tiles of mesh based NoC architecture is proposed. These approaches are based on the task priority list and the platform priority list. According to the simulation results, the MDB2-Spiral (scenario5) algorithm provides more efficient results in comparison with some mapping algorithms, e.g., Genetic, random, Spiral and other scenarios of this paper. In addition, significant energy consumption savings can be achieved by the MDB2-Spiral mapping algorithm.