Simulation study for suppressing corner effect in a saddle MOSFET for Sub-50 nm high density high performance DRAM cell transistor

In this work, the reasons for the abnormal corner effect, its impact on the saddle MOSFET device characteristics, and possible approaches to suppress it are examined through simulation. Effectively suppressing the abnormal corner effects is important for application in sub-50 nm high density high performance DRAM cell transistor.