4H-SiC LJFET-based power IC using depletion load

In this abstract, we describe the design and modeling of a super buffer gate drive circuit using low-voltage (LV) VC-LJFETs of enhancement and depletion modes. In contrast to the first power IC, this design eliminates the need for on-chip resistors, which raise concerns for resistance accuracy and matching due to epilayer doping, depletion cut-in and misalignment issues. In this work, normally-on VC-LJFETs with shorted gate and source terminals are used as transistor loads, whose nonlinear I-V characteristics allow faster switching of the power device in comparison to a DC-equivalent resistor-load driver. The exclusive use of VC-LJFET structure for the power device and gate driver assures process compatibility and monolithic fabrication of the power IC.