Scaling of the SOI field effect diode (FED) for memory application

Memory arrays consume a very large area in chip designs, yet memory cell scaling lags significantly transistor scaling. With transistor channel lengths in the nanoscale regime, the six transistor static random access memory cell (6T-SRAM) and the (one transistor/one capacitor) dynamic memory (DRAM) both suffer from excessive leakage current. Consequently, there is a widely recognized need for urgent progress in memory technology. The thin capacitively coupled thyristor (TCCT) based memory cell (T-RAMs) approach is a most promising, CMOS compatible alternative to the standard cell both for SRAM and DRAM cell designs. However, the T-RAMs demand the precise control of doping profiles of the p-n junctions so as to achieve correct breakdown characteristics. To address these difficulties, the authors explored the possibility of replacing the thyristor with a suitable field effect diode (FED), which displays similar current-voltage characteristics without suffering from the above technological drawbacks. In this paper, the scalability of the FED was studied and compare it with TCCT by numerical simulations.