Demonstration of the fault recognition and recovery of FPGA circuits by means of Cytokine-Formal Immune Networks

Self-repairing systems under system failure, return service faster by means of a recovery oriented design. A self-repairing system is composed of a system, which in its most general form is composed by an input and an output, a self-testing module and a recovery module. The self-testing module requires a test pattern generator and a test response evaluator. The test pattern generator should generate an optimal minimal set of test vectors. The test response evaluator should be fast in order to shorten the time the system is out of service. The recovery module could have options like: reset of the system, select another operation through an operation selector or reconfigure the system. Reconfiguration could take place placing the same operation in another circuit area or another operation in the same circuit area. Last option is possible in FPGA circuits thanks to reconfiguration support. But, FPGAs are sensitive to radiation and also prone to errors. Approaches like triple modular redundancy, embryonics or immunotronics are an attempt to deal with faults, nevertheless they do not consider standard FPGAs. The author proposed an approach that focuses fault tolerance from the design perspective. First an optimal minimal set of test vectors is intended to be obtained. Second, a fast evaluation technique for the test response evaluator is searched. And third, a procedure for error correction is drafted. The demonstration presents an algorithm and an architecture based on the cytokine - formal immune networks for preparing the set of test vectors and built a suitable fault recognition unit which supports recovery. A self-repairing system is shown by means of a hardware implementation in a FPGA board.