A timestamping method using reduced cost ADC hardware

For many semiconductor devices, time stability and relative time location of electrical events is critical; clocks need to strobe data when the data is valid. This fundamental performance is indicative of both the general quality of manufacture and the suitability of a particular device. Parametric measures might include duty cycle variation, peak-to-peak jitter, RMS jitter and minimum pulse width. As increasingly complex timing generation circuits are implemented with mixed analog and digital technology, more sophisticated testing requires a time sense between events (e.g. cycle-to-cycle jitter, period jitter and deterministic jitter.) Traditional time measurement instruments are often challenged to perform the latter type tests due to physical constraints driving slow re-arm times relative to high data and clock rates, sometimes in excess of 10 GHz. Even for the former tests, test time will directly scale to the number of edges required, multiplied by the re-arm time. This paper presents a method to efficiently measure many events in succession for non-repetitive clocks and data with a fast re-arm time. By separating events in time across several channels but maintaining their relative timing, the individual events occur at a relatively lower time rate on each channel. The slower events can be conditioned in the analog domain and recorded with less sophisticated hardware and avoid averaging. A detailed discussion of the hardware and software methods is discussed and the resulting accuracy and throughput performance presented.