A 300 MHz 64 b quad-issue CMOS RISC microprocessor

This quad-issue custom VLSI implementation of the Alpha architecture delivers 1200 MIPS/600 MFLOPS (peak) performance. The 16.5/spl times/18.1 mm/sup 2/ die contains 9.3 M transistors. It is built in a 3.3 V 4-layer metal, 0.5 /spl mu/m CMOS process. The upper metal layers are used primarily for power, clock, and global bus distribution. The chip is packaged in a 499-pin ceramic IPGA with 205 pins dedicated to VDD/VSS. The package includes a copper tungsten intrusive slug that provides a low thermal resistance between the die and a detachable heat sink. The chip is air cooled and dissipates 50 W at 300 MHz. 160 nF of on-chip decoupling capacitance controls power-supply noise.