A low-power 4K point FFT processor for CMMB OFDM receiver system

This paper presents a 4096-point FFT processor for CMMB receiver system, in which dual-path pipelined shared memory architecture is employed. With a data reordering for receiver, an elaborate memory configuration scheme, single-port SRAM can be adopted without degrading throughput rate, with small area and lower power dissipation. In addition, the Signal-to-Quantization Noise Ratio (SQNR) of a 4 K-point fixed-point FFT can achieve 48.7 B with the wordlength of 12 bit.