A cost efficient LDPC decoder for DVB-S2

Based on the Min-Sum algorithm, this paper proposes an LDPC decoder integrating the TDMP schedule, which could achieve low complexity as well as good performance. The LDPC decoder is for DVB-S2, which includes 11 kinds of code rates with a block size of 64800. Based on SMIC 0.13µm standard CMOS process, the LDPC decoder has an estimation area of 14mm², a throughput of 135Mbps with a frequency of 105MHz and maximum iteration number of 30,which shows advantage over previous DVB-S2 LDPC decoders¹.