Design of 16-bit 400MSPS current steering D/A converter

In this study, design of a 16-bit, 400MSPS high-speed high-resolution current steering D/A converter is described. With pipelined thermometer decoding, multi-stage synchronous latch, current-source matching array design, two-stage active cascade design, and current switch nonlinear capacitor bootstrapping compensation technologies, DAC dynamic performances at high frequency are improved. The DAC uses the design in 0.25 um CMOS process technology. Its die size is 4.84 mm × 4.9 mm. High-frequency broadband SFDR>63 dBc@Fout=(331/1024) × 400 MHz & F_sample =400 MHz.