An architecture of fuzzy logic controller with parallel defuzzification

In the hardware implementation of an FLC (fuzzy logic controller), it is natural to introduce parallelism. Many researchers have designed and implemented FLCs with parallel architectures, where the processing time has radically decreased. However, the defuzzification procedure is difficult to parallelize because it requires large hardware components such as multipliers and dividers, and inter-communication between processing elements. Usually, the resulting fuzzy sets are sequentially defuzzified by additional defuzzification processors or lookup tables. We propose a parallel defuzzification algorithm and a simple network architecture. This algorithm performs the MOA (median-of-area) defuzzification method. The proposed architecture has a SIMD (single instruction multiple data) structure, that consists of a CU (control unit) and 128 PEs (processing elements). We design and implement the FLC using FPGA chips. The FLC has other powerful features such as an active-rule driven architecture and a minimized membership memory. When the FLC operates at 10 MHz, for a 2-input/1-output, 64 rules fuzzy inference problem, it has a processing speed of 526 K FLIPS. This is nearly 70 times faster than the Pentium-90.