A novel technique for upgrading the performance of FPGA-based legacy systems

Field Programmable Gate Arrays are frequently used in avionics signal processing applications due to their potential for substantial processing speedup. FPGAs can be particularly valuable in DSP applications because these tend to be data flow type problems. However, many systems employ FPGAs that are older and offer lower performance and fewer resources, making them difficult to upgrade as more powerful and processing-intensive algorithms become available. This problem is exacerbated by the fact that the process of translating all or part of a complex application to an FPGA is complicated, time-consuming, and prone to error, and the result often does not represent the optimum design in terms of performance, size, power consumption, and accuracy. As a result, a large, complex application may not fit on a legacy system or meet critical timing requirements. Commercially available automated design tools cannot guarantee that they represent the most optimal solution. In this paper we describe a new approach to automated FPGA hardware design that guarantees optimized hardware in terms of speed, power, area, or any combination of these characteristics while substantially decreasing design time. The approach also guarantees the correctness of the design in terms of the original algorithm, which may speed any required certification or recertification.