Optimistic Peripheral Devices Performance by Virtual Regionalized Network-on-Chip

The multi-core has become inevitable and on-chip communications network to replace the traditional structure of the shared bus architecture has become the trend of the computer science development. Obverse that a general router in mesh NoC have four access interfaces, at the border of the chip does not take full advantage of these interfaces, that is say, only router in middle of chip fully utilized. Hence, we have the main peripheral controllers are directly connected to the router of these unutilized interfaces, means border unutilized routing interface. Then the paper proposes an architecture that the NoC mesh network is divided into several virtual regions which take advantage of applications characteristics to adapt the IO external communication requirements and of the applications self internal communication patterns. Suit for parallel programming model, high I/O demanding system and utilize the existing hardware resources, our scheme is promising.