A generalized hardware implementation of MIMO fading channels

Based on field programmable gate array (FPGA) and general computer platform, a generalized emulator of spatiotemporally correlated multiple/input multiple/output (MIMO) channel is realized. In detail, a 2times2 MIMO channel emulator, including 24 clusters delay and 20 sub-paths delay per cluster, using 41% of on-chip block memories, 97% of dedicated multipliers, and 53% of configurable slices of Xilinx Virtex-5 XC5VLX330T-2 FPGA, is proposed. Verification of the proposed MIMO channel fading emulator is accomplished by the realization of dynamic spatial channel model (SCM) and Kronecker model. The hardware platform provides powerful tools for performance simulation of the MIMO wireless links, testing of the wireless communication equipment and evaluation of base-band algorithms.