Generic array-based MPSoC architecture

Interest in NoC prototyping is continuously growing, as many recent processing chips are multi-cores. Prototyping such systems is a quite complex task. High level simulations validate the functionality of an application but do not guarantee functionality of all possible dedicated implementations. FPGA implementations give a higher level of confidence at low level, but their limited size only permits to validate parts of complex SoCs. We propose an array-based MPSoC architecture, matching requirements of applications where the data can be split into several subsets and processed in parallel, as is the case in numerous video processing algorithms. Since the array size is configurable, we are able to validate the low level FPGA implementation with a limited number of processing elements, but keep a high confidence in the full size final implementation. We have physically implemented a 2×2 Xtensa core system in a Virtex II Pro vp100 and tested it in a real time application.