SiGe bipolar transistor modeling for a full chip ESD simulation

A new compact model compatible with industry standard circuit simulation tools is developed to predict the current and voltage characteristics of SiGe bipolar transistors beyond their breakdown. This is a region of interest for circuit simulations during ESD (electro-static discharge) events. The enhanced bipolar models are benchmarked versus device-level TLP (transmission line pulse) measurements and used in full-chip ESD event simulation for identifying design weaknesses and optimizing emerging circuit designs for ESD robustness.