A 1.8GHz SelfCalibrated PhaseLocked Loop with Precise I/Q Matching

This paper describes a 1.8-GHz self-calibrated phase-locked loop (PLL) implemented in 0.35-µm CMOS technology. The PLL operates as an edge-combining type fractional- N frequency synthesizer using multiphase clock signals from a ring-type voltage-controlled oscillator (VCO). A self-calibration circuit in the PLL continuously adjusts delay mismatches among delay cells in the ring oscillator, eliminating the Cractional spur commonly found In an edge-combing fractional divider due to the delay mismatches. With the calibration loop, the fractional spurs caused by the delay mismatches are reduced to - 55 dBc, and the corresponding maximum phase offsets between the multiphase signals is less than 0.2°. The frequency synthesizer PLL operates from 1.7 to 1.9 GHz and the closed-loop phase noise is -105 dBc/Hz at 100-kHz ofTset from the carrier. The overall circuit consumes 20 mA from a 3.0-V power supply.