A CMOS Frequency Synthesizer with an InjectionLocked Frequency Divider for a 5GHz Wireless LAN Receiver

A fully integrated S-GHz phase-locked loop (PLL) based frequency synthesizer is designed in a 0.24 µm CMOS technology. The power consumption of the synthesizer is significantly reduced by using a tracking injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. On-chip spiral inductors with patterned ground shields are also optimized to reduce the veo and ILFD power consumption and to maximize the locking range of the ILFD. The synthesizer consumes 2S mW of power of which only 3.8 mW is consumed by the VCO and the ILFD combined. The PLL has a bandwidth or 280 kHz and a phase noise of -101 dBc/Hz at 1 MHz offset frequency, The spurious sidebands at the center of adjacent channels are less than -54 dBc.