Design of PLL-Based Synchronous PWM Oscillator in Class-D Power Amplifier

To minimize the effect of cross talk in monolithic stereo class D power amplifier, one improved scheme in stereo application with dual-chips is presented. Pulse Width Modulation (PWM) in master and salve chip should be synchronized each other for decreasing distortion, so a phase locked loop (PLL) -based synchronous oscillator is designed in class-D power amplifier chip. When power supply is 5.5 V, input frequency is 1 KHz and output power is 3.7 W in 4 Ohm load, the total harmonic noise (THD) of amplifier is less than 1% and efficiency is about 90%. The class-D amplifier quiescent current is 1.9 mA and shutdown quiescent current is 0.5 muA.