A Method of Phase-Locked Loop Performance Testing

In general, CPU may upgrade its frequency by the PLL (phase-locked loop), but the cost of testing is very expensive for high frequency signals. This paper introduces the method that inserts test logics in the CPU to implement its PLL performance testing. It is very easy to implement, and reduces effectively test costs in the case of low hardware overheads. The result shows that the test logics can fulfill the PLL performance testing.