Breakdown voltage improvement of standard MOS technologies targeted at smart power

This paper presents and discusses trade-offs of three different design techniques intended to improve the breakdown voltage of n-type lateral medium power transistors to be fabricated in a conventional low cost CMOS technology. A thorough analysis of the static and dynamic characteristics of the modified structures was carried out with the support of a two-dimensional device simulator. The motivation behind this work was the construction of a low cost smart power microsystem, including control, sensing and protection circuitries, targeted at an electronic ballast for efficient control of the power delivered to fluorescent lamps.