Optimization of FIR filters in subexpression space with constrained adder depth

A popular technique in the design of multiplierless FIR filters explores the common subexpression sharing when the filter coefficients are optimized. In these techniques, the coefficient multiplier are realized as a multiplier block (MB) with shared shifters and adders. Many researches showed that the power consumption of a MB is often not simply proportional to the number of adders but is rather very much dependent on the adder depth of every coefficient. In this paper, an optimization technique is proposed to design the MB with constrained adder depth to achieve low power consumption. Numerical examples show that the proposed algorithm generates filters using less adders with low adder depth.