Corrections to “On the Suitability of a High-$k$ Gate Dielectric in Nanoscale FinFET CMOS Technology”

In the above titled paper (ibid., vol. 55, no. 7, pp. 1714-1719), the propagation delays in Table III are incorrect, being too long by a factor of two. Furthermore, there was a typo in the table title. The corrected table and title are presented here.