On the Design of a Suitable Hardware Platform for Protocol Stack Processing in LTE Terminals

In this paper we present a design methodology for the identification and development of a suitable hardware platform (including dedicated hardware accelerators) for the data plane processing of the LTE protocol stack layer 2 (L2) in downlink direction. For this purpose, a hybrid design approach is adopted allowing first investigations of future mobile phone platforms on the system level (using virtual prototyping) combined with more accurate power-area explorations of hardware accelerators on the architectural level. Additionally, we show the employment of an LTE data generator peripheral, realizing L2 uplink processing and thus enabling platform analyses in a closed virtual environment. Furthermore, a modeling technique for a fast and efficient design of virtual hardware accelerator peripherals is demonstrated. A reasonable hardware/software partitioning can thereby be achieved early in the design phase. Once the system architecture is settled and thus the solution space is reduced, VHDL models of the accelerators are developed in order to find a suitable hardware implementation for LTE terminals based on timing constraints by system level simulations. As a case study, the LTE ciphering scheme, including the Advanced Encryption Standard (AES), is applied. We show results of our methodology by developing a deciphering hardware accelerator that enables the LTE protocol stack to process data rates of 100 Mbit/s and beyond.