FPGA-Accelerated Baseband Design and Verification of Broadband MIMO Wireless Systems

The design of communication systems has become more challenging as product complexity and cost pressures have increased and time-to-market has shortened more than ever before. Performance verification of the physical layer (PHY) of wireless communication networks under various radio propagation conditions is a computationally-daunting process. Bit-true software-based simulation of the PHY layer on workstations is becoming prohibitively time-consuming. This makes hardware-accelerated prototyping and verification of the PHY layer an increasingly attractive alternative. This paper presents a bit error rate tester (BERT) for baseband performance verification of multiple antenna (MIMO) systems over accurate radio propagation channel models. This BERT integrates all of the required modules of a typical PHY layer onto a single field-programmable gate array (FPGA). The proposed BERT system significantly decreases the test time compared to conventional software-based verification, hence increasing designer productivity.