Notice of Violation of IEEE Publication Principles: Time minimization of hybrid BIST for systems-on-chip

Notice of Violation of IEEE Publication Principles. "Time Minimization of hybrid BIST for systems-on-chip" by I. Popa, D. Cazacu in the 31st International Spring Seminar on Electronics Technology (ISSE 2008), 2008, pp. 153 - 158 After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE's Publication Principles. This paper contains significant portions of original text from the paper cited below. The original text was copied with insufficient attribution (including appropriate references to the original author(s) and/or paper title) and without permission. Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following article: "Test Time Minimization for Hybrid BIST of Core-Based Systems" by Gert Jervan, Petru Eles, Zebo Peng, Raimun Ubar, Maksim Jenihhin in the 12th IEEE Asian Test Symposium (ATS03), 2003, pp. 318 - 323.
We concentrate on hybrid BIST optimization for multi-core designs. As total cost minimization for multi-core systems is an extremely complex problem and is rarely used in reality, the main emphasis here is on test time minimization under memory constraints with different test architectures. The memory constraints can be seen as limitations of on-chip memory or ATE memory, where the deterministic test set will be stored, and therefore with high practical importance. We will concentrate on one large classes of test architectures and we assume that every core is equipped with its own pseudorandom pattern generator and only deterministic patterns have to be transported to the cores. For this architecture we will describe test-per-clock as well as test-per-scan application schemes.