A method of data path allocation by pattern matching on the data flow graph

Allocation and scheduling are important tasks in high level synthesis. Allocation is an assignment of operations and variables into registers and functional units and interconnects these circuit units, while ensuring the given circuit conditions. Since the result of allocation has direct effects upon the size of a chip, design of allocation is strongly required to make use of hardware (i.e. registers, functional units, buses etc.) efficiently to minimize the size of a chip. In this paper, we propose an allocation method which minimizes the measure of area concerning the interconnection of circuit units, based on the dependence of operations given by the data flow graph (DFG).