The design of clock distribution in the parallel/interleaved sampling system

The paper introduced the mathematical model in both time and frequency domain of parallel/interleaved sampling system, the total gain error, phase shift error, aperture jitter error of multi-channel sampling scheme are all involved. The critical layout techniques of a hi-speed and hi-resolution analog-to-digital conversion circuit are also provided. At last, a 4-channel interleaved sampling clock circuit with the jitter level of sub-picosecond is given, whose phase noise and jitter test results are also shown.