Fault modeling of differential ECL

The paper deals with testability analysis of differential ECL. The logic behaviour and the drop in performance concerning a very detailed list of possible defects of a high speed ECL-Design was examined. The test circuit, an AND gate (bandwidth: dc to 3.4 Gb/s), was designed taking into account a low power consumption and a small overhead as it is used for weighted random pattern generation and signature analysis (edge counting) within a Built-In-Self-Test (BIST)-Architecture. It was realized using a 1.2 /spl mu/m bipolar technology. It is shown that defects in differential ECL devices may cause redundant or delay faults in respect to operation speed.