Active-area-segmentation (AAS) technique for compact, ESD robust, fully silicided NMOS design

This paper describes a layout technique to optimize the ESD performance per area for fully silicided NMOS devices by segmenting the active area of drain and source regions. Efficient multi finger triggering is achieved by intrinsic inter-finger-coupling through the bulk enabled by compact finger design. The technique is successfully applied in a 0.13 um and a 0.18 um CMOS technology obtaining HBM ESD capability of up to 8.6 V/um².