Analysis of ESD protection components in 65nm CMOS technology: Scaling perspective and impact on ESD design window

A scaling analysis of fundamental ESD components (low voltage transistors, N-well diodes, interconnects and thin dielectrics) for the last three CMOS technology nodes (130 nm, 90 nm and 65 nm) targeting the same low-power applications is presented. The impact of technology scaling on the ESD design window will be discussed.