Experimental results of an analog current-mode ART1 chip

A hardware implementation of a modified version of the ART1 algorithm has been built. The modified algorithm preserves all the computational properties of the original one but allows a more efficient hardware implementation. A prototype chip has been fabricated in a standard 1.5 /spl mu/m low cost single poly CMOS process. The chip implements an ART1 network with 100 F1 nodes and 18 F2 nodes. Therefore, it can cluster input patterns with 100 binary pixels into up to 18 categories. The estimated time needed to classify and learn an input pattern is less than 1 /spl mu/s, which means a computing power of 1.8 Gconnections/s. The chip has a die area of 1 cm/sup 2/ and is mounted on a 120-pins PGA package. The operation of the chip is analog, mainly based on currents additions and a Winner-Take-All action, but all the inputs and outputs are digital voltages, making the chip digitally compatible. Experimental results of time measurements, current mismatches among the synapses and the global operation of the system are available.