A 0.13µm CMOS preamplifier for low level signal acquisition systems

This paper describes a preamplifier, which is based on switched capacitor techniques in order to minimize both offset and noise; small sensitivity to process variations, mismatch and common mode signals are obtained by using a differential circuit topology. Simulations using a proprietary Intel 0.13 mum CMOS process show an offset voltage of 6 muV, a CMRR of 90 dB and a power consumption of 60 muW.