Notice of Violation of IEEE Publication Principles: Cost minimization for ASIC hybrid BIST designs

Notice of Violation of IEEE Publication Principles

"Cost Minimization for ASIC Hybrid BIST designs"
by I. Popa, A. Zafiu, D. Cazacu
in the 32nd International Spring Seminar on Electronics Technology (ISSE 2009), 2009, pp. 1 - 6

After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE's Publication Principles.

This paper contains significant portions of original text from the papers cited below. The original text was copied with insufficient attribution (including appropriate references to the original author(s) and/or paper title) and without permission.

Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following articles:

"Test Cost Minimization for Hybrid BIST"
by Gert Jervan, Zebo Peng, Paimund Ubar
in the International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2000), 2000, pp. 283 - 291

and

"Using Tabu Search Method for Optimizing the Cost of Hybrid BIST"
by Raimund Ubar, Helena Kruss, Gert Jervan, Zebo Peng
in the 16th Conference on Design of Circuits and Integrated Systems (DCIS 2001), 2001, pp. 445 - 450


Are presented different methods for a hybrid BIST cost optimization for single-core designs. For selecting the optimal switching moment from the pseudorandom test mode to the stored test mode, two algorithms were proposed for calculating the complete cost curve of the different hybrid BIST solutions. The first one is a straightforward method based on using traditional fault simulation and test pattern generation. The second one is based on fault table manipulations and uses test compaction. The experimental simulated results demonstrate the feasibility of the approach and the efficiency of the fault table based cost calculation method.