Performance and power consumption trade-offs for a VLIW DSP

Since performance and power consumption optimizations are crucial issues in embedded systems, it is necessary to find a trade-off between these optimization goals. This paper explores the performance and power trade-offs of VLIW processor, specifically the Texas Instruments TMS320C6416T DSP. We evaluate the effect of the global performance optimizations as well as a specific architecture feature on the power consumption of the targeted processor while running typical digital signal and image processing algorithms. We assess the specific C64x+ architecture feature, software pipelined loop (SPLOOP), effect on the power consumption and the performance as well. The binaries used in this study were generated using the Texas Instrument C/C++ Compiler, which allows control over the whole set of optimizations.