Heavy ion testing and 3D simulations of Multiple Cell Upset in 65nm standard SRAMs

Heavy ions experiments are carried out on commercial 90 nm and 65 nm SRAMs. The contribution of single and multiple cell upsets are discussed as a function of the LET for different memory cell areas and for triple well usage. Once again, well engineering plays a key role on MCU and SEE response of SRAM. Full 3D TCAD simulations investigate the occurrence of parasitic bipolar effect.