Experimental analysis of RESET resistance distribution in phase change memories

Phase change memories (PCMs) are promising candidates for multilevel storage, thanks to the wide programming window. The multilevel approach requires good control of the programmed cell resistance. For any multilevel programming strategy, the RESET operation plays a key role for the accuracy of the intermediate programmed resistance levels. In this paper, we analyze the impact of the applied RESET pulse amplitude and the fabrication process spreads on the resistance distribution obtained after the RESET operation. To this end, we propose a model to estimate the impact of device parameter spreads on the amorphous cap thickness and, hence, on the cell resistance obtained after a RESET operation. The proposed model is verified by means of experimental characterization on a PCM cells array.