A probabilistic approach for reducing connectivity in multiple bus systems

This paper presents a probabilistic approach for reducing the number of connections in a multiple bus system while achieving the performance of a full bus connection system. The memory modules are partitioned into some equal sized groups. A subset of buses are connected to each of these groups and a set of common buses are connected to all the groups; and the buses are connected to all the processors. We use a probabilistic approach to determine the number of full connection buses. We consider all possible request patterns and determine the number of common buses required for each of those patterns. For each request pattern we consider the corresponding request probability and determine the statistical average of the number of common buses required. We assume a uniform distribution for processor to memory requests. We show that only with a few common buses the performance, in terms of memory bandwidth, remains the same as that of full bus connection system. The connection complexity is however reduced significantly. Our results are supported by simulations.