An algorithm and design procedure for high speed carry select adders using FPGA technology

A new algorithm and design procedure is introduced for the construction of a 32 bit adder Implementing the Field Programmable Gate Arrays technology. The algorithm is based on the carry select technique with operands partitioned into very fine slices for quick response. The slice carries, however, are propagated in a multiplexer based structure using a parallel processing technique. The aim of this parallel processing is to produce the final carry terms logarithmically, rather than linearly. It is shown that this logarithmic approach substantially reduces the carry propagation delays as the data size becomes larger, and in fact, for each doubling of the operand size only one gate delay is added to the overall time for the addition. The design is simulated and carried out using Actel/TI FPGA product libraries.