Computing exact path delay-fault coverage using OBDDs

Symbolic representation of path delay-faults can achieve high degree of compaction relative to more explicit forms. Large numbers of path delay-faults exist in common digital circuits. Ordered binary decision diagrams (OBDDs) provide a convenient data structure to represent these large number of path delay faults during the process of fault simulation computing the path delay-fault coverage for a given delay test-set. We present some experimental results from applying these algorithms to common benchmark examples that demonstrate the viability of our approach.