Design of a programmable slew-rate op amp

This paper presents the design of a CMOS programmable slew rate operational amplifier. The amplifier proposed in this paper is capable of providing an additional programmable bias current which can be linearly controlled by an external 4 bit digital signal. The circuit designed for slew rate programmability is based upon a newly proposed concept, that is a switched parallel current subtraction circuit with an adaptive biasing technique. By utilizing the newly designed circuit, it was verified that the slew rate was linearly controlled and power dissipation was optimized. If the programmable slew rate amplifier is employed in a data converter, its data conversion time can be easily controlled.