A flexible gate array for high speed and high density applications

A scaleable gate array has been designed in half-micron CMOS for a wide range of high-speed and high-density applications. Transistor size and position within the basecell provide an efficient implementation of flip-flops, combinational gates, and memory. Design benchmarks have demonstrated 2700 gates/mm/sup 2/ routed density in a 0.5 /spl mu/m TLM CMOS gate array. Compared to previous 5 V 0.7 /spl mu/m gate arrays, the new basecell provides a 2.5/spl times/ density improvement, 30% speed-up, and 70% lower power. NAND-2 delays are 170 ps (FO=2, 3.3 V). Metal-programmable two-port SRAMs feature 3.9 ns typical access times. The new architecture has been implemented in a CMOS gate array family which offers up to 1.15 million available gates and 700 I/O positions.