Accurate analysis of CMOS inverter driving transmission line based on FDTD

This paper introduces a numerical method for time domain analysis of the inverter driving interconnect in CMOS digital integrated circuits. To include the carriers' velocity saturation effect of short-channel devices, the alpha-power law model is used for MOS transistor modeling. Moreover, interconnect is modeled as transmission line, which is required in deep submicron technologies. Based on detailed analysis of inverter operation and FDTD analysis of transmission line, the accurate time domain response and 50% delay can be achieved by iterative computation. The error of the proposed method is within 5% and the runtime is only one-sixth compared with SPICE.