Development of GE's plastic thin-zero outline package (TZOP) technology

One of the major obstacles impeding the wide spread use of multichip technology in the commercial electronics industries is the procurement and yield of bare chips. This area includes the reluctance of IC manufactures to supply bare chips due to the lack of standards, the difficulties associated with testing bare chips and their lack of confidence in the abilities of the MCM fabricators to assemble bare chips into MCMs without damaging good parts. Another aspect of die procurement is that bare chips are not generally available in TAB or flip-chip solder bump configurations. A highly flexible multichip interconnect approach has been developed with un-matched performance advantages that will be applicable to a wide range of commercial applications. Quick turn prototyping is made easy with maskless processing, electronic data entry, and integrated CAD CAM environment from customers, to engineering, to procurement and to manufacturing. This technology provides the highest density electronic packaging with its edge to edge chip spacing, its top mounted component capability and its 3D stacking and substrate thinning options. The basic electronic interconnection technology involves: plastic encapsulated single or multichip modules; flexible, conformable multichip on flex assemblies; non-planar single or multichip modules molded into conformal surfaces; and ball grid array MCM assemblies. These interconnect structures will be applied to digital, RF, analog, power conversion and mixed mode circuits.