A NoC performance evaluation platform supporting designs at multiple levels of abstraction

Network-on-Chip (NoC) has been proposed as a new solution to deal with the global communication problem of complex System-on-Chip (SoC), which faces huge design challenges. A performance evaluation tool is essential for designers to explore the design space, verify functionality and estimate performance of designs. This paper presents a performance evaluation platform of NoC, which can measure and present performance of NoC designs at transaction-level, register-transfer-level and application-level of abstraction. Based on the hierarchical progressive abstraction approach, the platform has been built using SystemVerilog-based Transaction Level Modeling. This platform enables to generate various traffic patterns and support evaluation of multiple levels of service in NoC. Additionally, it is applicable to networks with arbitrary size, topology and multiple interface protocols. The effectiveness and correctness of this platform are verified by evaluating and analyzing specific NoC instances at the end of the paper.