Designs of switched-capacitor comparator using low-voltage floating-gate MOS transistors

A new structure of comparator circuit based on a pair of complementary floating-gate (FG) MOS transistors is introduced in this paper. Our main design purpose is to focus on low complexity structure and low operating supply voltage. The comparator comprises two stage amplifiers: differential input stage and gain stage. Simulation results from Hspice on 0.25 mum TSMC CMOS technology and 1.5 V power supply are demonstrated. Power consumption of 0.89 muW can be achieved on the operation at 10 MHz and input offset of 50 muV.