Fast timing simulation for submicron hot-carrier degradation

This paper presents a new fast timing reliability simulator ILLIADS-R which can simulate hot-carrier degradation in very large integrated circuits. A region wise-quadratic model is used to fit submicron transistor I-V curves. Using quasi-static models, ILLIADS-R accurately simulates hot-carrier damage in both pMOS and nMOS transistors of large scale CMOS integrated circuits.