A novel technique for parallel computations using associative dataflow processor

The current microelectronics technology is expected to have the capability of 50-100 million transistors on a single chip by the year 2000. Such an on-chip hardware capacity motivates the development of a new generation of faster and more intelligent computers incorporating efficient techniques to handle computations. The prevalent concepts of control-flow and data-flow to build computers have their limitations and weaknesses in exploiting parallelism to the utmost limit. Therefore, a novel technique to handle parallel computations, called associative dataflow, is presented in this paper. In the proposed model of computation, the need for tokens is eliminated. The processing of a dataflow graph is accomplished in two phases. (1) The search phase: assuming the dataflow graph to be upside-down, each node at the top of the hierarchy, called the parent, looks for its descendants, called children, which are at the bottom of the hierarchy. This facilitates each node to know its data and destination(s) in the system. (2) The execution phase: the operations are performed, but now there is no delay in creating or matching tokens. This approach eliminates the major bottleneck in dataflow architectures, concerning the matching of tokens and the enhancement of their performance. Preliminary results have indicated a faster execution speed and higher ALU utilization for the proposed model compared to the conventional dataflow model. These results forecast a promising future for the associative dataflow model of computation.