Throughput analysis of input queueing ATM switches under imbalanced traffic loading

Throughput performance of an N/spl times/N ATM (for B-ISDN) switch with input queueing is examined. Two architectures are considered: shared input memory and dedicated input memory. Input traffic streams are mutually statistically independent, with identical output port distributions. Arriving cells are stored in the input memory. At any time slot, N cells residing in the memory are considered for transfer into the output queues. However, only cells with distinct output addresses can be transferred into the output queue. We define q/sub 0/ as a probability that 0 cells arrive at the input port during a slot. The probability that a cell is destined to an output port i is denoted as P/sub i/. Let us define P/sub M/=max(P/sub i/, i=1, ..., N). We show that the maximum normalized throughput per port is upper bounded by (1-q/sub 0/)/(NP/sub M/). The carried throughput levels per output ports are also evaluated. This new bound is shown to be very tight for P/sub M//spl ges/2/N. We also show, that for input queueing shared memory switch configurations, the same result holds also for a more general traffic loading model, under which traffic streams feeding different input ports may be correlated and governed by different output port distributions.