Crosstalk avoidance and error-correction coding for coupled RLC interconnects

On-chip interconnect delay and crosstalk noise have become an important factor for performance and signal integrity as a result of increase in device densities and operating clock frequency in deep sub-micrometer (DSM) VLSI circuits. With faster rise times and lower resistance, interconnects exhibit significant inductive effect compared to capacitive effect. Therefore, various existing coding techniques for capacitive crosstalk reduction in resistive-capacitance (RC) interconnects are not suitable for resistive-inductance-capacitance (RLC) interconnects in high-speed circuits. At the same time, on-chip interconnects are susceptible to various DSM noise sources. Error-correction coding (ECC) improves interconnect-reliability against DSM noise. This paper proposes a modified boundary shift coding technique that simultaneously addresses inductance-dominant cross-talk noise reduction and error-correction for coupled RLC interconnects. Results show that proposed coding achieves up to 50% reduction in additional wiring requirement.